1. Field of the Invention
The present invention relates to a transistor having a hetero-junction, and more particularly to a semiconductor device that enables the achievement of a base having the desired resistance and good repeatability, and to a method for manufacturing such a semiconductor device.
2. Related Art
A method for manufacturing a bipolar transistor having an AlGaAs or GaAs hetero junction in the prior art is described with reference made to FIG. 5 and FIG. 6.
On a GaAs substrate 101 a first n-type GaAs layer 102 of 500 nm thickness, a second n-type GaAs layer 103 of 500 nm thickness, a p-type GaAs layer 104 of 50 nm thickness, an n-type Al.sub.0.2 Ga.sub.0.8 As layer 106 of 30 nm thickness, and a third n-type GaAs layer 107 of 20 nm thickness are sequentially grown, using an MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy) process. The doping of each layer is made so as to enable functioning as a device. Next, a photolithographic process is used to form a photoresist layer 108 having a dimension of approximately 0.8 .mu.m thickness (FIG. 5(a)).
Next, using a gas mixture of, for example, SF.sub.6 and BC1.sub.3, selective dry etching is done so as to etch the third GaAs layer 107, thereby forming an n-type GaAs emitter contact layer 127. When this is done, etching is stopped at the surface of the n-type Al.sub.0.2 Ga.sub.0.8 As layer 106 (FIG. 5(b))
Next, sulfuric acid and hydrogen peroxide or the like are used to perform wet etching of the n-type Al.sub.0.2 Ga.sub.0.8 As layer 106, and expose the surface of the p-type GaAs layer 104 (FIG. 6(a)). When this is done, an etching rate of the n-type Al.sub.0.2 Ga.sub.0.8 As layer 106 is equal to that of the p-type GaAs layer 104, so that the amount of etching of the n-type Al.sub.0.2 Ga.sub.0.8 As layer 106 is controlled by the etching time, and part of the p-type GaAs layer 104 is etched in the process. Additionally, because this is anisotropic etching, variations occur in the emitter dimensions.
In the case in which the above-noted etching shown in FIG. 5(b) and FIG. 6(a), the overall etching time becomes long, and fine control of the emitter dimensions becomes difficult. Therefore, there is a need to perform separate etching of the n-type Al.sub.0.2 Ga.sub.0.8 As layer 106 and the p-type GaAs layer 104 and, thereby causing an increase in the number of process steps.
Finally, an n-type GaAs sub-collector layer 122, an n-type GaAs collector layer 123, a p-type GaAs base layer 124, an emitter electrode 129, a base electrode 130, and a collector electrode 131 are formed using conventional processes, thereby fabricating the transistor (FIG. 6(b)).
The second prior art example shown in FIG. 7 is a transistor that is disclosed in the Japanese Examined Patent Publication (KOKOKU) No.6-12778.
In the hetero-bipolar transistor shown in FIG. 7, an n.sup.- - type GaAs collector layer 223 with a donor concentration of 1.times.10.sup.16 atoms/cm.sup.3, a p.sup.- type GaAs base layer 224 with an acceptor concentration of 1.times.10.sup.18 atoms/cm.sup.3, an undoped Al.sub.0.4 Ga.sub.0.6 As emitter barrier layer 225 of thickness 10 nm, and an n.sup.- type Al.sub.0.2 Ga.sub.0.8 As emitter layer 226 with a donor concentration of 5.times.10.sup.17 atoms/cm.sup.3 are formed onto an n.sup.+ - type GaAs substrate 201 having a donor concentration of 1.times.10.sup.18 atoms/cm.sup.3. In this drawing, the reference numeral 231 denotes a collector electrode, the reference numeral 230 is a base electrode, and the reference numeral 229 is an emitter electrode.
In this prior art example, carriers which are injected into the base layer 224 from the emitter layer 226, passing through the emitter barrier 225, are accelerated by the band discontinuity between the emitter barrier 225 and the base layer 224, so as to pass through the base layer 224 at a high speed, thereby enabling ultra-highspeed operation.
As described above, in the first prior art example, when removing the emitter layer, the base layer is also etched. Therefore, there is an increase in the resistance of the base region and the occurrence of variations of the base resistance. Additionally, because it is difficult to control emitter dimension, there is the added problem of the occurrence of variations of the emitter current value.
In the second prior art example as shown in FIG. 7, a thin undoped Al.sub.0.4 Ga.sub.0.6 As emitter barrier layer 225 is sandwiched between an Al.sub.0.2 Ga.sub.0.8 As emitter layer 226 and a GaAs base layer 224, however, it is impossible to use an undoped Al.sub.0.4 Ga.sub.0.6 As emitter barrier layer 225 as an etching stopper, therefore, it is impossible to achieve selective etching of the Al.sub.0.2 Ga.sub.0.8 As emitter layer 226 with respect to the undoped Al.sub.0.4 Ga.sub.0.6 As emitter barrier layer 225. Thus, this structure has the same drawback as that of the first prior art example.
Accordingly, it is an object of the present invention to provide a bipolar transistor having a hetero-junction, in which patterning of an emitter layer does not affect the dimension of the base layer therebelow, thereby preventing an increase in the resistance of the base layer, and also in which dimensional control of the emitter is facilitated. It is a further object of the present invention to provide a method for manufacturing the above-noted semiconductor device.